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Open 3D


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Contact: OPEN_3D@cea.fr



Preliminary results using a 3D integration technology for hybrid pixel detectors designed for particle physics and imaging experiments :

Minapad2012_presentation-2.pdf Minapad 2012 presentation (2.45 MB)


Conference program :

MiNaPAD Forum 2012 conference program.pdf Conference program - MiNaPAD 2012 (2.92 MB)


More information : http://france.imapseurope.org/




• What is 3D Integration ?


In electronics, a 3D integrated component is a device in which at least 2 active layers have been vertically integrated in order to achieve a new component or a system.
Those layers could be homogeneous or heterogenous in term of component function, material, substrate sizes or technological node.


• What are the main interest of 3D integration ?

  • form factor decrease:
    final device miniaturization (X,Y, Z)

  • performance improvement:
    - resistance and parasitic capacitance decrease, signal propagation rate increase.
    - bandwidth increase
    - reduction of power consumption

  • heterogeneous integration:
    - logic / analog components
    - memories
    - sensors / MEMS
    - passives components
    - energy sources
    …

  • cost reduction
    - active silicon surface reduction
    - advanced & mature technologies partitioning
    - legacy production line reuse


Open 3D Leti component



• What are the key interest for you to work with Open 3D ?

  • to boost your innovation by:
    - product performance improvement
    - targeting new products, new applications, new markets and new customers

  • to promote your products with the opportunity to:
    - customizing your components
    - limiting the cost
    - optimizing the cycle time of the project
    - having a global offer including design, technology, test. Packaging is also possible with a partner.
    - achieving proof of concept (small quantity of wafers), prototyping or small volume production

  • accessing innovative technologies
    Technological modules catalogue:
catalogue modules technos.pdf Technological offer (1.23 MB)


  • to collaborate with international experts in the following areas:
    - design / masks
    - technologies & processes
    - metrology / characterization
    - reliability

  • to benefit to a high level quality approach:
    ISO 9001 certification



• What are the Open 3D means & facilities ?

  • international environment of the Minatec campus

  • 10 000 m² of clean rooms and laboratories supporting 200mm by now and 300 mm wafer format at the end of 2012

  • high level technological platforms:
    - design
    - MEMS 200
    - 3D 300 line (end of 2012)
    - test and characterization



• How to work with Open 3D ?


 Leti's Open 3D offer



Publications


• 3D Integration technology for hybrid pixel detectors used in particle physics experiments

Abstract Minapad 2012_version finale.pdf Abstract MiNaPAD 2012 (11.11 kB)



• Process and RF modelling of TSV last approach for 3D RF interposer - IITC 2011 / Dresden (D)

IITC 2011-TSV last RF modeling-LETI-abstract.pdf Abstract-IITC 2011-TSV last RF modeling-LETI (5.09 kB)



• A Silicon Platform With Through-Silicon Vias for Heterogeneous RF 3D Modules - EUMW 2011 / Manchester (UK)

EuMW 2011-TSV last RF-ST-LETI-abstract.pdf Abstract-EuMW 2011-TSV last RF-ST-LETI (6.22 kB)



• Reliability Study of 3D-WLP Through Silicon Via with Innovative Polymer Filling Integration - ECTC 2011 / Buena Vista lake (USA)

ECTC 2011-TSV last filling-LETI-abstract.pdf Abstract-ECTC 2011-TSV last filling-LETI (6.26 kB)



• Hermetic Wafer-Level Packaging development for RF MEMS switch - ESTC 2010 / Berlin (D)

ESTC 2010-TSV last for MEMS-LETI-abstract.pdf Abstract-ESTC 2010-TSV last for MEMS-LETI (13.04 kB)



• Process Solutions and Polymer Materials for 3D-WLP Through Silicon Via Filling - ECTC 2010 / Las Vegas (USA)

ECTC 2010-TSV last filling-LETI-abstract.pdf Abstract-ECTC 2010-TSV last filling-LETI (5.52 kB)


• Development and Characterisation of a 3D Technology Including TSV and Cu Pillars for High Frequency Applications - ECTC 2010 / Las Vegas (USA)

ECTC 2010-TSV Last-LETI-abstract.pdf Abstract-ECTC 2010-TSV Last-LETI (7.28 kB)



• Development and Characterisation of High Electrical Performances TSV for 3D Applications - EPTC 2009 / Singapore

EPTC 2009-TSV last-LETI-abstract.pdf Abstract-EPTC 2009-TSV last-LETI (7.88 kB)



• Low Cost Lithography Solution for Advanced Packaging and Application to Through Silicon Via Process - EPTC 2008 / Singapore

EPTC 2008-TSV last litho process-LETI-abstract.pdf Abstract-EPTC 2008-TSV last litho process-LETI (6.16 kB)



• Enabling Technologies for 3D integration: From Packaging Miniaturization to Advanced Stacked ICs - IEDM 2008 / San Francisco (USA)

IEDM 2008-3D Integration-LETI-abstract.pdf Abstract-IEDM 2008-3D Integration-LETI (5.76 kB)



• Through Silicon Vias Technology for CMOS Image Sensors Packaging - ECTC 2008 / Buena Vista lake (USA)

ECTC 2008-TSV last for CIS-LETI-abstract.pdf Abstract-ECTC 2008-TSV last for CIS-LETI (5.60 kB)



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