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Contact: Carlo Reita (carlo.reita@cea.fr)
Moving circuits into three dimensions
New processes — from three-dimensional multi-gate structures to ultrathin silicon and germanium layers — push transistor technology forward.
Leti is helping our industrial partners lay the foundation for future products.
Teams work on circuit design and simulation, the micro/nanoelectronics effort focuses on the physical devices themselves.
As soon as new materials or new structures offer improved performance, their integration in a CMOS flow is immediately studied.
The semiconductor industry has pushed the limits of planar CMOS technology
This integration focus has become especially critical in recent years. New materials, new structures, and process technologies that were once laboratory curiosities are being considered for mainstream production.
As transistors shrink, controlling device variability becomes more difficult. Atomic scale fluctuations in dopant density can cause performance shifts.
One solution — Leti's 25nm fully depleted silicon-on-insulator transistor — reduces the problem by using an undoped silicon channel.
The gate-first structure, implemented with an HfO2 gate dielectric and mid-gap TiN gate electrode, achieved the best transistor matching ever reported at these dimensions. An SRAM cell is now in development.
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