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Contact: Laurent Clavelier (laurent.clavelier@cea.fr)
Going beyond silicon to create new applications
Leti spinout SOITEC has become the world leader in silicon-on-insulate (SOI) substrates. Today, Leti and Soitec are developing a wide range of innovative substrates for new applications and capabilities, including logic, networking, and photovoltaics.
Cost reduction linked to Germanium substrates:
-collaboration between Leti and Soitec using Smart CutTM technology
-development of a new nucleation substrate concept for the epitaxy of III-V materials
-economic innovation relying on reusing germanium layers across multiple wafers.
-an approach that is compatible with recent developments in inversed metamorphic structures
Optical networking can help networks keep up with rapidly increasing amounts of data, using micro-devices to switch, filter, and manipulate optical data streams at gigahertz frequencies. Multilayer substrates of silicon, silicon oxide, and lithium niobate show extremely good performance across very wide frequency ranges.
Improving calculation speed through better management of power dissipation due to heat on chips:
-integrating thin layers of diamond as buried insulation in SOI substrates
-improving heat evacuation at the substrate level due to the heat conduction characteristics of diamond that allow for improved circuit functions
Leti - A unique R&D expertise:
-one of the few organizations in the world with the tools and skills to make such innovative materials production-worthy
-the most advanced techniques including customized ion implant, deposition, bonding, thinning, and metrology equipment
-more Leti-developed materials reaching the market every year in a variety of commercial devices.
New studies at Leti
-A multi-year 50-person collaboration with SOITEC is accelerating commercial viability of multiple materials innovations. These include ultra-thin buried oxides (UTBOx), photovoltaic devices, and silicon-on-lattice-engineered substrates (SOLES) that are used to manufacture hybrid radio frequency circuits such as CMOS on SOI and HBT on III-V.
-Leti and STM have set new standards for copper-to-copper bonding of devices and wafers, achieving state-of-the-art electrical performance with a no-force, low-temperature, atmospheric process that can be economically applied in 3D packaging.
-In 2008 we developed the ability to create cavities inside monocrystalline silicon MEMS devices, for use in ultra-sensitive accelerometers. The process unites molecular-level bonding with wafer grinding to achieve unprecedented results.
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