The shrinking of electronic circuitry on CMOS devices is no longer sufficient for increasing device performance and reducing power consumption. Advanced devices are showing problems of crosstalk, power consumption and RC delay despite the use of copper interconnects.

At the same time, the process of improving performance by “stacking” several devices on top of one another is gaining momentum.

-Today, Leti is developing new interconnect techniques to increase device functionality:

- packaging and heterogeneous integration

- memory

- component logic

- component RF

- sensors to provide a complete system or subsystem in one package

These solutions produce smaller form factors, lower costs and reduce time to market.

The Leti Toolbox

Leti’s technical strategy is to develop a 3D toolbox for both on-chip CMOS interconnects and packaging, to help cover the wide range of potential applications. The toolbox offers a variety of solutions that can be mixed and matched to meet the specific application needs of our partners. These include deep silicon etch and metallization processes that allow interconnects to pass through silicon substrates, such as through-silicon vias (TSV).
In 2008, Leti transferred several technology platforms and processes to its industrial partners, including:

- a process for TSV CMOS imaging sensors that is being used in production

- stacking of Flash memory on CPU technology for Smart Cards that uses µinsert technology developed at Leti.